Initial Study of a Phase-Aware Scheduling for Hardware Transactional MemoryTomoki TAJIMI,
Anju HIROTA,
Ryota SHIOYA,
Masahiro GOSHIMA,
Tomoaki TSUMURA Proc. IEEE Pacific Rim Conf. on Communications, Computers and Signal Processing (PacRim 2017),
Victoria ,
6p.
(Aug. 2017)
10.1109/PACRIM.2017.8121912 CSDLPaperSlide
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h5-index: 12 (2016)
Exclusive Control for Compound Operations on Hardware Transactional MemoryKeisuke MASHITA,
Anju HIROTA,
Tomoaki TSUMURA Proc. 2nd IEEE Nordic Circuits and Systems Conference (NorCAS 2016),
POSTER PAPER,
Copenhagen ,
6p.
(Nov. 2016)
10.1109/NORCHIP.2016.7792919 CSDLDBLPPaperPosterBlog
A Concurrency Control in Hardware Transactional Memory Considering Execution Path VariationAnju HIROTA,
Keisuke MASHITA,
Tomoaki TSUMURA Proc. 4th Int'l Symp. on Computing and Networking (CANDAR'16),
REGULAR PAPER,
Hiroshima ,
pp.77–83
(Nov. 2016)
2016年度 情報処理学会東海支部 学生論文奨励賞 受賞 10.1109/CANDAR.2016.0026 CSDLDBLPPaperSlideBlog
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A.R.: 34.2%